In order to alleviate the problem of excessive noise and excessive power consumption introduced by longdistance transmission of highfrequency clock signals in multichannel SerDes, a lowpower lowjitter twostage phaselocked loop applied to multichannel serial interface is designed, Simultaneously, this design is used to transmit the lowfrequency clock signal (3.125 GHz) generated by the firststage LC oscillator phaselocked loop to each channel transceiver, this signal is taken as the secondlevel reference signal, and then a smallarea ring oscillator phaselocked loop is used to produce an orthogonal highfrequency clock (12.5 GHz). This structure reduces the distance that the highfrequency clock transmits over long distances on the chip, and improves the clock quality of the transceiver. In addition, this technology avoids the use of highfrequency buffers and reduces power consumption. In order to further reduce the noise performance, a sampling phase detector is designed in the secondstage phaselocked loop. This technology improves the noise performance of the secondstage ringvibration phaselocked loop by means of nofrequency phase discrimination. The overall power consumption of the clock generator circuit is 100 mW, the phase noise of the firststage phaselocked loop is -125 dBc/Hz, and the phase noise of the secondstage ring oscillator circuit is -79 dBc/Hz at 1MHz. The overall jitter of the clock signal generated by the circuit is 2.7 ps. The quadrature clock skew is within 300 fs.