This paper presents a novel technique to reduce the number of operations in Multiplierless implementations of linear DSP transforms based on shifting and adding , CSD ,and sub-expressions. The complexity of multiplier blocks can be significantly reduced by using an efficient number system. First it gives the 10 bits CSD representation and definition of Sub-expressions. Then Statistical Characterization of CSD Code is studied , it found that the five-term Sub-expressions elimination . Through the design and implementation of FIR, our method will use the less adders than ordinary schemes.