Aimed at the characteristic that the error rate of NAND FLASH increases with the increase of the time of use, a highspeed parallel RCRF+BCH error correction scheme with stronger error correction capability while using fewer parity bits is proposed. The idea of RCRF corrects some of the initial erasure errors, and then cascades BCH codes to correct the remaining bit errors, which can greatly ensure the accuracy of data and significantly improve the reliability of the storage system. The article explains in detail the encoding and decoding principles and execution steps of the highspeed parallel algorithm. In the BCH part, the iBM key equation solving algorithm without inversion that consumes less hardware resources is used, and then the different paths of the error position polynomial are listed through derivation Several-deterministic forms facilitate the application of combinatorial logic to describe them, thus avoiding the complicated iterative judgment process and further improving the decoding speed. And adopt the modular processing method and the pipeline operation mode to optimize the BCH codec structure. Finally, it was implemented on FPGA platform hardware and simulated to verify the effectiveness of this scheme.