In view of solving the problems of large clock jitter in CDR circuit of SerDes, a new highspeed and high linearity phase interpolator is designed. On the basis of the nonlinear mechanism of the input control code and the output clock phase of the phase interpolator, and through calculating the inverse function relationship between the output clock phase and the weight of the tail current source, array parameters of the tail current source in the phase interpolator are designed accurately, realizing the high linearity relationship of the phase interpolator at high speed and effectively improving the CDR recovery Clock jitter performance. In this paper, the technology of a 22 Gb/s SerDes receiver based on CMOS 65nm process designed is verified. The simulation results show that the linearity of the phase interpolator and the jitter performance of CDR recovery clock are increased by 55.1% and 22.5% respectively.