The timing logic problem of gate-level information flow is investigated based on basic GLIFT theory, the implementation of four typical triggers is given when the system clock is trusted.The gate-level information flow tracking logic area, time delay and power consumption are evaluated for the test vectors of the IWLS set using Synopsys compiler to generate 90 nm standard library files. Compared with the original GLIFT code, the average area of the circuit is reduces more than 50%, time delay is reduces about 13% when timing logic is introduced. The obtained area and time delay information reflect the complexity of fine-grained control of information flow; the simulation results of power consumption comparison show that the power consumption of the tracking logic reaches about 5 to 20 times the original logic, the power consumption issues need further research and optimization.