文章摘要
刘洋1,李杰1,李金强2,李炳臻1,赵计贺1.一种基于RCRF+BCH算法的NAND FLASH纠错方案的FPGA设计与实现[J].空军工程大学学报:自然科学版,2020,21(6):46-52
一种基于RCRF+BCH算法的NAND FLASH纠错方案的FPGA设计与实现
FPGA Design and Implementation of a NAND FLASH Error Correction Scheme Based on RCRF + BCH Algorithm
  
DOI:
中文关键词: 纠错系统  Reset Check Reverse Flag算法  Bose Chaudhuri Hocquenghem  NAND FLASH
英文关键词: error correction system  Reset-Check-Reverse-Flag  N10Bose-Chaudhuri-Hocquenghem  NAND-FLASH
基金项目:国家自然科学基金(61973280);中国博士后科学基金(2019M661069)
作者单位
刘洋1,李杰1,李金强2,李炳臻1,赵计贺1 1.中北大学仪器科学与动态测试教育部重点实验室 太原 030051 2.山东航天电子技术研究所 山东烟台 264000 
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中文摘要:
      针对目前NAND FLASH随着使用时间的增长误码率随之增高的特性,提出了一种在使用更少校验位的情况下纠错能力更强的高速并行RCRF+BCH纠错方案,初步用RCRF的思想对部分初始擦除错误进行纠正,然后级联BCH码纠正剩余的位错,很好地保证数据的准确性,显著提高存储系统的可靠性。首先详细阐述了该高速并行算法的编译码原理和执行步骤,在BCH部分中使用消耗更少硬件资源的无求逆的iBM关键方程求解算法,然后推导出错误位置多项式不同路径的几种确定形式,方便应用组合逻辑对其进行描述,避免了复杂的迭代判断过程,进一步提高了译码速度,并采用模块化的处理方式和流水线的操作模式优化了BCH的编译码结构。最终在FPGA平台硬件实现并仿真验证了此方案的有效性。
英文摘要:
      Aimed at the characteristic that the error rate of NAND FLASH increases with the increase of the time of use, a high speed parallel RCRF+BCH error correction scheme with stronger error correction capability while using fewer parity bits is proposed. The idea of RCRF corrects some of the initial erasure errors, and then cascades BCH codes to correct the remaining bit errors, which can greatly ensure the accuracy of data and significantly improve the reliability of the storage system. The article explains in detail the encoding and decoding principles and execution steps of the high speed parallel algorithm. In the BCH part, the iBM key equation solving algorithm without inversion that consumes less hardware resources is used, and then the different paths of the error position polynomial are listed through derivation Several-deterministic forms facilitate the application of combinatorial logic to describe them, thus avoiding the complicated iterative judgment process and further improving the decoding speed. And adopt the modular processing method and the pipeline operation mode to optimize the BCH codec structure. Finally, it was implemented on FPGA platform hardware and simulated to verify the effectiveness of this scheme.
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