文章摘要
郭凯乐, 王和明, 刘涛, 陆德超.基于高速SerDes中非等值尾电流源技术的新型高线性度相位插值器设计[J].空军工程大学学报:自然科学版,2020,21(4):61-67
基于高速SerDes中非等值尾电流源技术的新型高线性度相位插值器设计
A Non-Equivalent Tail Current Source Based New Phase Interpolator with High Linearity for High-Speed SerDes
  
DOI:
中文关键词: 时钟数据恢复电路  非等值电流源  相位差值器  线性度
英文关键词: clock and data recovery circuit  non-equivalent current source  phase interpolator  linearity
基金项目:国家重点研发计划(2018YFB2202300)
作者单位
郭凯乐, 王和明, 刘涛, 陆德超 空军工程大学防空反导学院 西安, 710051 
摘要点击次数: 32
全文下载次数: 26
中文摘要:
      为解决高速串行接口(SerDes)中时钟数据恢复电路(CDR)的恢复时钟抖动较大的问题,设计了一种基于非等值尾电流源技术的新型高速高线性度相位插值器。该技术在分析相位插值器输入控制码和输出时钟相位产生非线性机理的基础上,通过计算晶体管电路中插值器输出时钟相位与尾电流源权重的反函数关系,精确设计了相位插值器中尾电流源阵列参数,实现了高速率下相位插值器的高线性度关系,有效提高了CDR恢复时钟抖动性能。通过设计一款基于CMOS 65 nm工艺的22 Gb/s SerDes接收机对该技术进行了验证。电路后端仿真结果表明:相较于传统结构,该相位插值器线性度提高了55.1%,CDR恢复时钟的抖动性能提高了22.5%。
英文摘要:
      In view of solving the problems of large clock jitter in CDR circuit of SerDes, a new high speed and high linearity phase interpolator is designed. On the basis of the nonlinear mechanism of the input control code and the output clock phase of the phase interpolator, and through calculating the inverse function relationship between the output clock phase and the weight of the tail current source, array parameters of the tail current source in the phase interpolator are designed accurately, realizing the high linearity relationship of the phase interpolator at high speed and effectively improving the CDR recovery Clock jitter performance. In this paper, the technology of a 22 Gb/s SerDes receiver based on CMOS 65nm process designed is verified. The simulation results show that the linearity of the phase interpolator and the jitter performance of CDR recovery clock are increased by 55.1% and 22.5% respectively.
查看全文   查看/发表评论  下载PDF阅读器
关闭